fpga串口通信的verilog驱动编程解析.docx
fpga串口通信的veri1og驱动编程解析串口的全程为串行接口,也称为串行通信接口,是采用串行通信方式的扩展接口。与串口对应的并行接口，例如高速型和DA,这些都是用的并行接口，而且在编程也简单一些。串口有一下特点:(1)通信线路简单，只要一-对传输线就可以实现双向通信。(2)布线简单，成本低。通信距离长，可以实现数米到数千米的通信距离。(4)传输速率慢。常见的串口速率如4800,9600,115200bps,代表每秒钟发送多少bit数据，例如9600bps就代表1秒内发送9600bit数据。TransmitDirectionStartbit10000010DataParitybit(ifenab1ed)串口协议：协议比较简单，一般都是10位数据，1个起始位低电平，然后八个数据位，低位在前，一个奇偶校验位，平时一般不用，最后是一位停止位高电平，这样一帧数据发送结束。下面介绍一下我的程序框架:Uart_tx8ntro1:ControI_u2ck匚)rst_n匚bps_se1ect1.OuarttxenddataenUdrtdata7.0)dsse1e1Udr1ddt整体框架分为两个部分：一个是串口驱动部分另一个是串口数据控制部分。串口驱动部分负责串口驱动和波特率的选择，串口数据控制模块负责控制数据内容的控制和发送速度的控制。从上面时序图可以看出，每IOmS发送一帧数据，这里data_en负责波特率驱动使能，UarttxCnd有两个功能,一个是关闭data_en使能，另一个是给IOms计数器清零。/*Date:Description:2017-09-03Designforuart_,driver.*/modu1euart_tx_driver(/g1oba1c1ockinpute1k,/systemc1ockinputrstn,/syncreset/uartinterfaceoutputreguart_tx/userinterfaceinput1:0bps_se1ect,波特率选择input7:0uart_data,inputdata_en,发送数据使能outputreguart_tx_end）；/Funtion:参数定义parameterBPS_4800=14,d10417BPS.9600=14,d5208BPS_115200=14,d4349reg13:0entbpse1k9reg13:0bps9regbps_c1k_en;/bps使能时钟reg3:0bps_cntwire13:0BPS_C1K_V=bps»1/Funtion:波特率选择a1ways©(posedgee1kornegedgerst_n)beginif(!rst_n)bps<=1,d;e1seif(bps_se1ect=2,d)bps<=BPS_115200;e1seif(bps_se1ect=2,d1)bps<=BPS_9600;e1sebps<=BPS_4800;end/Funtion:波特率计数a1ways©(posedgee1kornegedgerst_n)beginif(!rst_n)cnt_bps_c1k<=1,d;e1seif(cnt_bps_c1k>=bps-1&&data_en=1,b)entbps_c1k<=c1;e1seentbps_c1k<=cnt_bps_c1k+d1;end/Funtion:波特率使能时钟a1ways©(posedgee1kornegedgerst_n)beginif(!rst_n)bps_c1k_en<=d;e1seif7cnt_bps_c1k=BPS_C1K_V-1)bps_c1k_en<=1,d1;e1sebps_c1k_en<=1,d;end/Funtion:波特率帧计数a1ways©(posedgee1kornegedgerst_n)beginif(!rst_n)bps_cnt<=Td0;e1seif(bps_cnt=11)bps_cnt<=d;e1seif(bps_c1k_en)bpscnt<=bpsent+d1;end/Funtion:uarttxenda1ways©(posedgee1kornegedgerst_n)beginif(!rst_n)uart_tx_end<=d;e1seif(bps_cnt=11)uart_tx_end<=d1;e1seuart_tx_end<=1,d;end/Funtion:发送数据a1ways©(posedgee1kornegedgerstn)beginif(!rst_n)uart_tx<=1'd1;e1secase(bps_cnt)4,d:uart_tx<=1,d1;4,d1:uart_tx<=d;/begin4,d2:uart_tx<=uart_dataO;/data4,d3:uart_tx<=uart_data1;4,d4:uart_tx<=Uart_data2;4,d5:uart_tx<=uart_data3;4,d6:uart_tx<=uart_data4;4,d7:uarttx<=uartdata5;4,d8:uarttx<=uartdata6;4,d9:uarttx<=uartdata7;4,diO:uart_tx<=1;/stopdefau1t:uart_tx<=1;endcaseendendmodu1e*Date:2017-XX-XXDescription:Designfor*/modu1euart_tx_contro1(/g1oba1c1ockinpute1k/systemc1ockinputrst_n/syncreset/userinterfaceoutputreg7:0uart_data,outputregdata_en,inputuart_tx_end/Funtion:参数定义parameterDE1AY_10MS500000reg31:0ent10mswirede1ayIOrnsdone/datadefinereg31:0cnt_1s;/Funtion:cnt_10msa1ways(POSedgee1kornegedgerstn)beginif(!rstn)entIOms<=d;e1seif(cnt_10ms=DE1AY_10MS-1&&uart_tx_end=d1)cnt_10ms<=d;e1secnt_10ms<=cnt_10ms+d1;endassignde1ay_10ms_doned1:1,d;(cnt_10ms=DE1AY_10MS-1)?/Funtion:data_ena1ways(posedgee1kornegedgerstn)beginif(!rst_n)data_en<=1'd;e1seif(de1ay_10ms_done)data_en<=d1;e1seif(uart_tx_end)data_en<=1'd;end/数据测试/Funtion:cnt_1sa1ways(POSedgee1kornegedgerstn)beginif(!rst_n)cnt_1s<=1,d;e1seif(cnt_1s=49_999_999)cnt_1s<=1,d;e1secnt_1s<=cnt_1s+1,d1;end/Funtion:uartdataa1ways(posedgee1kornegedgerstn)beginif(!rst_n)uart_data<=1'd;e1seif(uart_data>=10)uart_data<=1,d;e1seif(cnt_1s=49_999_999)uart_data<=uart_data+d1;endendmodu1e黄飞
