【开发教程3】AI语音人脸识别（会议记录仪／人脸打卡机）-定时器.docx
CC3200AI实验教程疯壳开发板系列W olverine-Team2018/07/1：目录1.1 寄存器11.2 实验现象19官网地址：http:www.fen>k/.club购买链接：http:官方 QQ 群：193836402定时器1.1 寄存器CC3200包含4个32位用户可编程通用定时器(TimerAO3),通用定时器可以对定时器输入引脚的外部事件进行计数或定时。每个定时器模块包含2个16位的定时/计数器(TimerA和TimerB),可以作为定时器或事件计数器独立工作，也可以作为一个32位定时器工作。CC3200的定时器具有多种操作模式：16位或32位可编程单次定时器；16位或32位可编程周期定时器；16位通用定时器，带8位预分频器；16位输入边沿计数或时间捕捉模式，带8位预分频器；16位脉冲宽度调制模式(PWM),带8位预分频器和软件可编程输入。具有以下特性：a、向上或向下计数；b、16个16位或32位捕捉比较PWM (CCP)引脚;c、可以确定产生定时器中断到进入中断服务程序(ISR)的时间；d、可以触发使用DMA的高效传输；e、系统时钟运行(80MHz)。GPTMCFG寄存器主要是配置通用定时器模块的全局操作。确定通用定时器工作于32位模式还是16位模式。该寄存器中的值只能是在GPTMCTL寄存器中的TAEN和TBEN两位被清零时改变。如图1.0.1所示。Table 9-9. GPTMCFG Register Field DescriptionsBitFieldTypeResetDescription31-3RESERVEDROh2-0GPTMCFGR/WOhGPTM Configuration The GPTMCFG values are defined as follows:1h-3h = Reserved 5h - 7h = ReservedOh = For a 16/32-bit timer, this value selects the 32-bit timerconfiguration.4h = For a 16/32-bit timer, this value selects the 16-bit timerconfiguration. The function is controlled by bits 1:0 of GPTMTAMRand GPTMTBMR.图1O1 GPTMCFG寄存器20位：写入0,配置为32位定时器模式；写入4,配置为16位定时器模式。GPTMTAMR寄存器配置是基于GPTMCFG寄存器的配置来进行选择的。在PWM模式中，置位TAAMS位、清除TACMR位和配置TAMR为0x01或者0x02o寄存器如图1.0.2所示，位定义如图1.0.3所示。rlyuic D-v. r i m i /nmr rvyyioib3130292827262524RESERVEDR-Oh2322212019181716RESERVEDR-Oh15141312111098RESERVED| TAPLOTAMRSUTAPWMIETAILDR-OhR/WQhR/W-OhR/W-OhR/WQh76543210RESERVEDTAMIETACDIR | TAAMSTACMIRTAMRR-OhR/W-OhR/W-OhR/W«OhR/WQhFVW-Oh图102 GPTMTAMR寄存器官网地址：http:/www.fenRke.dub 淘宝店： 官方 QQ 群：1938364023Table 9-10. GPTMTAMR Register Field DescriptionsBitFieldTypeResetDescription31-12RESERVEDROh11TAPLOR/WOhGPTM Timer A PWM Legacy OperationOh = Legacy operation with CCP pin driven Low when theGPTMTAILR is reloaded after the timer reaches 0.1h = CCP is driven High when the GPTMTAILR is reloaded after thetimer reaches 0.10TAMRSUR/WOhGPTM Timer A Match Register Update If the timer is disabled (TAENis clear) when this bit is set, GPTMTAMATCHR and GPTMTAPRare updated when the timer is enabled. If the timer is stalled(TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updatedaccording to the configuration of this bit.Oh = Update the GPTMTAMATCHR register and the GPTMTAPRregister, if used, on the next cycle.1h = Update the GPTMTAMATCHR register and the GPTMTAPRregister, if used, on the next timeout.9TAPWMIER/WOhGPTM Timer A PWM Interrupt Enable This bit enables interrupts inPWM mode on rising, falling, or both edges of the CCP output, asdefined by the TAEVENT field in the GPTMCTL register. In addition,when this bit is set and a capture event occurs. Timer Aautomatically generates triggers to the DMA if the trigger capability isenabled by setting the TAOTE bit in the GPTMCTL register and theCAEDMAEN bit in the GPTMDMAEV register, respectively. This bitis only valid in PWM mode.Oh = Capture event interrupt is disabled.1h = Capture event interrupt is enabled.Table 9-10. GPTMTAMR Register Field Descriptions (continued)BitFieldTypeResetDescription8TAILDR/WOhGPTM Timer A Interval Load Write Note the state of this txt has noeffect when counting up. The bit descriptions above apply if the timeris enabled and running. If the timer is disabled (TAEN is dear) whenthis bit is set. GPTMTAR GPTMTAV and GPTMTAPs. are updatedwhen the timer is enabled. If the timer is stalled (TASTALL is set),GPTMTAR and GPTMTAPS are updated according to theconfiguration of this bit.Oh = Update the GPTMTAR and GPTMTAV registers with the valuein the GPTMTAILR register on the next cycle. Also update theGPTMTAPS register with the value in the GPTMTAPR register onthe next cycle.1h = Update the GPTMTAR and GPTMTAV registers with the valuein the GPTMTAILR register on the next timeout. Also update theGPTMTAPS register with the value in the GPTMTAPR register onthe next timeout.7-6RESERVEDROh5TAMIER/WOhGPTM Timer A Match Internjpt EnableOh = The match interrupt is disabled for match events. Additionally,triggers to the DMA on match events are prevented.1h = An interrupt is generated when the match value in theGPTMTAMATCHR register is reached in the one-shot and periodicmodes.4TACDIRRA/VOhGPTM Timer A Count Direction When in PWM mode, the status ofthis bit is ignored. PWM mode always counts down.Oh = The timer counts down.1h = The timer counts up. When counting up( the timer starts from avalue of 0x0.3TAAMSR/WOhGPTM Timer A Alternate Mode Select The TAAMS values aredefined as follows: Note: To enable PWM mode, clear the TACMRbit and configure the TAMR field to 0x1 or 0x2.Oh = Capture or com
