Altera MAX 10 FPGA介绍（特性、优势、电路图）.docx

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1、A1tera公司的MAX10器件是单片非易失低成本可编逻辑器件(P1D),具有内部存储可配置的双闪存,用户闪存,集成了ADC,支持单片NiosII软件处理器,主要用在系统管理,I/O扩展,通信控制面板,汽车电子,工业控制和消费类电子产品.本文介绍了AIteraMAX10FPGA主要优势，A1teraMAX10FPGA开发套件主要特性,框图,元件分布图，电路图和主要元件表.MAX10devicesaresing1e-chip,non-vo1ati1e1ow-costprogrammab1eIogiCdevices(P1Ds)tointegratetheoptima1setofsystemcomp

2、onents.Thehigh1ightsoftheMAX10devicesinc1ude:Interna11ystoreddua1configurationf1ashUserf1ashmemoryInstantonsupportIntegratedana1og-to-digitaiconverters(ADCS)Sing1e-chipNiosIIsoftcoreprocessorsupportMAX10devicesaretheidea1so1utionforsystemmanagement,1/0expansion,communicationcontro1p1anes,industria1,

3、automotive,andconsumerapp1ications.A1teraMAX10FPGA主要优势：AdvantageSupportingFeatureSimp1eandfastconfigurationSecureon-dief1ashmemoryenab1esdeviceconfigurationin1essthan10msF1exibi1ityandintegrationSing1edeviceintegratingP1D1ogic,RAM,f1ashmemory,digita1signa1processing(DSP),ADC,phase-1ocked1oop(P11),an

4、dI0sSma11packagesavai1ab1efrom3mm3mm1owpowerS1eepmode一significantstandbypowerreductionandresumptionin1essthan1ms1ongerbattery1iferesumptionfromfu11power-offin1essthan10ms20-yearestimated1ifecyc1eBuiItonTSMC,s55nmembeddedf1ashprocesstechno1ogyHighproductivitydesigntoo1sQuartusIIwebedition(nocost1icen

5、se)Qsyssystemintegrationtoo1Digita1Signa1Processing(DSP)Bui1derNiosIIEmbeddedDesignSuite(EDS)A1teraMAX10FPGA开发套件TheA1teraMAX10FPGADeve1opmentKitprovidesafu11featureddesignp1atformbui1tarounda50K1ogice1ements(1Es)MAX10FPGA,optimizedforsystem1eve1integrationwithon-dieana1og-to-digita1converter(ADC),du

6、a1-configurationf1ash,andDDR3memoryinterfacesupport.Theboardfeatureson-boardUSB-B1asterTMII,high-speedmezanninecard(HSMC),andPmodCompatib1eexpansioncards,high-definitionmu1timediainterface(HDM1)output,anddua1Ethernetforindustria1Ethernetapp1ications.TheMAX10FPGADeve1opmentKitprovidestheperfectsystem

7、-1eve1prototypingso1utionforindustria1,automotive,consumer,andmanyothermarketapp1ications.Withthisdeve1opmentboard,youcan:Deve1opdesignsforthe10M50D,F484packageFPGAMeasuretheperformanceoftheMAX10FPGAana1og-to-digita1b1ockconversionInterfaceMAX10FPGAstoDDR3memoryat300MHzperformanceRunembedded1inUXusi

8、ngtheNiosIIprocessorInterfacetodaughtercardsandperiphera1susingHSMCandDigi1entPmodwCompatib1econnectorsMeasureFPGApower(VCC_COREandVCC_I0)usingthepowermonitorgraphica1userinterface(GUI)Reusethekit,SPCBboardandschematicasamode1foryourdesignTheMAX10FPGADeve1opmentKitinc1udesthefo11owing:RoHS-andCE-com

9、pIiantMAX10FPGdeve1opmentboardFeatureddevicesMAX10FPGA(10M50D,dua1supp1y,F484package)EnpirionEN2342QI4APowerSoCvo1tage-modesynchronousstep-downconverterwithintegratedinductorEnpirionEN6337QA3Ahigh-efficiencyPowerSoCDC-DCstep-downconverterswithintegratedinductorEnpirionEP5358xUI600mAPowerSoCDC-DCstep

10、-downconverterswithintegratedinductorMAXIICP1D-EPM1270M256C4N(On-boardUSB-B1asterII)ProgrammingandConfigurationEmbeddedUSB-B1asterII(JTAG)Optiona1JTAGdirectvia10-pinheaderMemorydevices64Mx161GbDDR3SDRAMwithsoftmemorycontro11er128Mx81GbDDR3SDRAMwithsoftmemorycontro11er512Mbquadseria1periphera1interfa

11、ce(quadSPI)f1ashmemoryCommunicationportsTwoGigabitEthernet(GbE)RJ_45portsOnemini-USB2.OUARTOneHDMIvideooutputOneuniversa1HSMCconnector(seeHSMCexpansioncards)Two12-pinDigi1entPmodwCompatib1econnectors(seePmodCompatib1eexpansioncards)Ana1ogTwoMAX10FPGADCSMAinputs2x10DCheaderPotentiometerinputtoDCOneex

12、terna116bitdigita1-to-ana1ogconverter(DAC)devicewithSMoutputC1ocking25MHzsing1e-ended,externa1osci11atorc1ocksourceSi1iConIabSc1ockgeneratorwithprogrammab1efrequencyGUISwitches,pushbuttons,jumpers,andstatus1EDsMini-USBcab1eforon-boardUSB-B1asterII2Apowersupp1yandcordFreeQuartusIIWebEditiondesignsoft

13、ware(down1oadsoftwareand1icensefromthewebsite)Comp1etedocumentationUsermanua1,bi11ofmateria1s,schematic,andboardfi1es图3.A1teraMAX10FPGA开发板系统框图图4.A1teraMAX10FPGA开发板电路图(1)图5.A1teraMAX10FPGA开发板电路图(2)图6.A1teraMAX10FPGA开发板电路图(3)图7.A1teraMAX10FPGA开发板电路图(4)图8.A1teraMAX10FPGA开发板电路图(5)图11.A1teraMAX10FPGA开发板电

14、路图（8）图12.A1teraMAX10FPGA开发板电路图（9）图13.A1teraMAX10FPGA开发板电路图（10）图14.A1teraMAX10FPGA开发板电路图（11）图15.A1teraMAX10FPGA开发板电路图（12）图16.A1teraMAX10FPGA开发板电路图（13）图17.A1teraMAX10FPGA开发板电路图（14）图20.A1teraMAX10FPGA开发板电路图（17）图21.A1teraMAX10FPGA开发板电路图（18）图22.A1teraMAX10FPGA开发板电路图（19）图23.A1teraMAX10FPGA开发板电路图（20）图24.A1teraMAX10FPGA开发板电路图（21）图25.A1teraMAX10FPGA开发板电路图（22）图28.A1teraMAX10FPGA开发板电路图(25)图29.A1teraMAX10FPGA开发板电路图(26)图30.A1teraMAX10FPGA开发板电路图(27)图31.A1teraMAX10FPGA开发板电路图(28)图32.A1teraMAX10FPGA开发板电路图(29)图33.A1teraMAX10FPGA开发板电路图(30)图34.A1teraMAX