【开发教程10】ARM功能手机-串口教程.docx

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1、串口实验教程疯壳开发板系列W olverine-Team2018/10/31目录第一节 串口硬件电路2第二节UART寄存器42.1 UART 介绍42.2 UART寄存器42.2.1 接收缓冲寄存器42.2.2 中断使能寄存器52.2.3 中断识别寄存器/FIFO控制寄存器62.2.4 通信线控制寄存器72.2.5 调制器控制寄存器72.2.6 通信线状态寄存器92.3 寄存器配置讲解11第三节UART实验12AA这里1胴 开机测试教程 整板资源介绍 开发环境搭建教程 快速上手教程 SIM900A通信实验代码及教程 TFT_LCD屏实验代码及教程 TP_Cap电容触摸屏实验代码及教程 W25Q

2、128-Flash实验代码及及教程 OV2640摄像头实验代码及教程 TF_Card接口实验代码及教程| MP3音乐播放实验代码及教程f SRAM实验代码及教程初级教程6主处I里器(SM324X) GPIO实验代码及教程 终端实验代码及教程 定时器实验代码及教程 串口实验代码及教程 ADC实验代码及教程i 12c实验代码及教程j SPI实验代码及教程 DMA实验代码及教程 FSMC实验代码及教程 DCMI实验代码及教程 SDIO实验代码及教程 USB实验代码及教程 STM资源整合I SIMCOM资源整合 Dialog资源整合 OmniVision资源整合 触摸屏实验 打接电话实验 收发短信实验

3、 音乐播放实验,拍照实验 手机与手环时间同步实验 读取手环步伐卡路里 心率测试实验 体温监测实验 NFC通信实验官网地址：http:www.fengke.dub购买链接：http:官方 QQ 群：193836402初级教程之蓝H他处理器(DA14580) GPIO实验代码及教程 中断实验代码及教程 定时器实验代码及教程 串口实验代码及教程 ADC实验代码及教程 12c实验代码及教程 SPI实验代码及教程蹴朝 datasheet数据手册 摄像头应用文档 BLE蓝牙低功耗应用文档 GSM/GPRS应用文档 MP3相关文档 充电电路相关文档 触摸屏相关文档 TF卡相关文档第一节串口硬件电路串口通过U

4、SB 口及手环下载调试线引出，连接MCU的P12与P13引脚，如下图所示：J3 CON3-71DA P13；DAPD1 IbGNDP1JPl _228DA P13DAP12第二节UART寄存器2.1 UART 介绍这个UART符合工业标准16550,并且可以和外围设备串行通信。主设备(CPU)通过APB总线将数据写进UART并且被转换成串行格式并且发送到目标设备。串行数据也可以通过UART被接收存储之后，主设备读取接收的数据。UART模块不支持DMA,但是它有内部FIFOs,并且支持硬件流控制信号(RTS,CTS,DTR,DSR)oUART模块有16字节的发送和接收FIFO；支持硬件流控制(C

5、TS/RTS)；影子寄存器来减少软件开销并且有可编程的软件复位；发送寄存器为空的中断模式；IrDA 1.0 SIR模式支持低功耗模式；可编程的字节属性、校验位和停止位(1,152);可以断开通信及检测通信线是否断开；中断优先级的识别；可编程的串行通信波特率。2.2 UART寄存器UART相关的寄存器比较多，所以我们只介绍常用的寄存器，其它的可以参考官方数据手册DA14580_DS_v3.l.pdf,位于目录：.WT开发板硬件资料。2.2.1接收缓冲寄存寤Table 81： UART_RBR_THR_DLL_REG (0x50001000)BitModeSymbolDescriptionRese

6、t15:8Reserved0x07:0R/WRBR_THR_DLLReceive Buffer Register: This register contains the data bytereceived on the serial input port (sin) in UART mode or theserial infrared input (sirjn) in infrared mode. The data in thisregister is valid only if the Data Ready (DR) bit in the Line sta-tus Register (LSR

7、) is set. If FIFOs are disabled (FCR0 set tozero), the data in the RBR must be read before the next dataarrives, otherwise it will be overwritten, resulting in an overrunerror. If FIFOs are enabled (FCR0 set to one), this registeraccesses the head of the receive FIFO. If the receive FIFO isfull and

8、this register is not read before the next data characterarrives, then the data already in the FIFO will be preservedbut any incoming data will be lost. An overrun error will alsooccur Transmit Holding Register This register contains datato be transmitted on the serial output port (sout) in UARTmode

9、or the serial infrared output (sir_out_n) in infraredmode. Data should only be written to the THR when the THREmpty (THRE) bit (LSR5) is set. If FIFOs are disabled(FCR0 set to zero) and THRE is set, writing a single charac-ter to the THR clears the THRE Any additional writes to theTHR before the THR

10、E is set again causes the THR data to beoverwntten. If FIFOs are enabled (FCR0 set to one) andTHRE is set, x number of characters of data may be written tothe THR before the FIFO is full. The number x (default=16) isdetermined by the value of FIFO Depth that you set duringconfiguration. Any attempt

11、to write data wtien the FIFO is fullresults in the write data being tost. Divisor Latch (Low): Thisregister makes up the lower 8-bits of a 16-bit. read/Write, Divi-sor Latch register that contains the baud rate divisor for theUART. This register may only be accessed when the DLAB bit(LCR7) is set. T

12、he output baud rate is equal to the senaldock (scik) frequency divided by sixteen times the value ofthe baud rate divisor, as follows: baud rate = (serial clock freq)/(16* divisor) Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud dock is disabled and no serialcommunicati

13、ons will occur. Also, once the DLL is set. at least8 clock cycles of the slowest DW_apb_uan clock should beallowed to pass before transmitting or receiving data.0x015:8位：保留不使用;7:0位：接收缓存寄存器。2.2.2 中断使能寄存器Table 82： UARTJER_DLH_REG (0x50001004)BitModeSymbolDescriptionReset一Reserved0x07R/WPTIME_DLH7Inter

14、rupt Enable Register: PTIME, Programmable THREIntermpt Mode Enable. This is used to enable/disable thegeneration of THRE Interrupt. 0 = disabled 1 = enabled Divi-sor Latch (High) Bit7 of the 8 bit DLH register.0x0一Reserved0x03EDSSLDLH3Interrupt Enable Register: EDSSI. Enable Modem StatusIntermpt. This is used to enable/disable tlie generation ofModem Status Interrupt. This is the fourth highest priorrtyinterrupt 0 = disabled 1 = enabled