基于vivado的fir ip核的重采样设计与实现.docx

《基于vivado的fir ip核的重采样设计与实现.docx》由会员分享，可在线阅读，更多相关《基于vivado的fir ip核的重采样设计与实现.docx（18页珍藏版）》请在第一文库网上搜索。

1、基于ViVadO的firip核的重采样设计与实现本文基于XiIir1X的IP核设计，源于音频下采样这一需求。创建vivado工程1.首先打开ViVad0,创建一个新的ProjeCt（勾选CreateprojectSUbdireCtOry选项），并将工程命填为firfi1ter。Fi1eF1owToo1s宣IndOWHe1PV1VXDOQuickStartPrO4.4i4*4NewProjectProjectNameEnteranameforyourprojectandspecifyadirectoryweretheproErojectname：IfirfiIterCreateNewProjec

2、tProject1ocation：homegscHRTasksCreateprojectsubdirectoryProjectwi11becreatedat：homegscFIRfrfi1terManageIPInformationCenter0Tc1Conso1estart_gui-1叩OperTypeaTc1CO1M1andhere2.选择工程创建的类型为RT1projecto在设计PCB会用到I/OPIanning这种类型，用在原理图和封装兼容性设计。Fi1eF1owToo1sWindowHe1pVIvXDOQuickStartPj0z4G1mIk41w11oNewProjectProj

3、ectTypeSpecifythetypeofprojecttocreate.CreateNewProjectRT1ProjectYouwi11beab1etoaddsources,createb1ockdesignsinIPIntegratiimp1ementation,designp1anningandana1ysis.HQonotspecifysourcesatthistimeTasksSManageIP(Eost-synthesisProject：Youwi11beab1etoaddsources,viewdeviceimp1ementation.DQnotspecifysources

4、atthistimeQI/OP1anningProjectOperDonotspecifydesignsources.Youwi11beab1etoviewpart/PaCkagInformationCenterQImportedProjectCreateaV1vadoprojectfromaSynp1rfy1XSTorISEProjectFi1e.QExamp1eProjectCreateanewVivadoprojectfromapredefinedtemp1ate.Tc1Conso1eStarJgUITypeaTc1Com11andhere3.选择芯片fami1y和封装，这种基于芯片选型

5、的工程，其能imp1ement的资源量受芯片自身容量限制。Fi1eF1owToo1sWindowHe1pV1W)ONewProjectDefau1tPartQuickStartexICreateNewProjectTasks线一ManageIPOperChooseadefau1tXihnxpartorboardforyourproject.ThiscanbecSe1ect：IPartSBoards-Fi1terInformationCenterTc1Conso1estart_guiPartI/OPinCountB1ockRAMsDSPsIfhxc7a200tfbg676-36763657402

6、6Cxc7a200tfbg676-267636574026cxc7a200tfbg676-21676365740262xc7a200tfbg676-167636574026Sxc7a200t1fbg676-1167636574026S瀚火IEG怛DefaIIit1ayO11t,X闻ProjectManagerfirfi1terSources一已X一冷口AddSourcesAddSourcesThisguidesyouthroughtheprocessofacOAddorcreateconstraintsIPIntegrator1CreateB1ockDesign，OpenB1ockDesign

7、GenerateB1ockDesignSimu1ation脸Simu1ationSettings疑RunSimu1ationRT1Ana1ysis6E1aborationSettings导OpenE1aboratedDesignSynthesisSynthesisSettingsARunSynthesisrOpenSynthesizedDesignImp1ementation的Imp1ementationSettingsARunImp1ementationtOpenImp1ementedDesign2填写创建的文件名为fir,类型是VeriIog。UseAddFi1etype：Veri1ogF

8、i1ename：Fi1e1ocation：:)-x口AddSourcesiAddorCreateDesignSourcesSpecifyHD1andnet1istfi1es,ordirectoriescontainingHD1andnet1istfi1es,toaddtoyourproject.Cresourcefi1eondiskandaddittoyourproject.oCreateSourceFi1eCreateanewsourcefi1eandaddittoyourproject.AddFi1esAddDirectoriesCreateFi1eScanandaddRT1inc1ude

9、fi1esintoproject回CopysourcesintoprojectE)AddsourcesfromsubdirectoriesBack定制FIRIP核1.类似创建designSoUrCe文件一样，单击PrOjeCtManager子菜单下的IPcata1og,在软件的右侧工作栏显示一个IPCataIog标签，在SCarCh过滤器中选择fir,双击F1RComPi1er选项。Ei1eEditF1owIoo1sWindOW1ayoutWeWHe1p上SS&X七S&EQIggDefaU1t1ayoUt/*F1owNavigator/ProjectManagerQProjectSetting

10、sqAddSources.1anguageTemp1atesIPCata1og,IPIntegrator常CreateB1ockDesign，OpenB1ockDesignGenerateB1ockDesign-Simu1ation5Simu1ationSettingsRunSimu1ationRT1Ana1ysisWE1aborationSettings.OpenE1aboratedDesignRunImp1ementationtOpenimp1ementedDesign-ProgramandDebugRitctroamCottinncProjectManagernrSourcesf.Des

11、ignSources2)(r.v)(1)ACoefficientFi1es(1)卜jConstraints57Simu1ationSources.sim_112).,(1ACoefficientFi1esProjeCoresHierarchyIPSourcesUbrariesCompi1eOrderASources.Temp1ates回回一Detai1s0FIRCompi1erVersion：7.2(Rev.4)Interfaces：AXI4-StreamIPProperties-ifDescription：TheXihnxFIRCompi1er1ogiCOREisamodu1eforgene

12、rationofhighspeed,compactfi1terimp1ementationsthatcanbeconfiguredtoimp1ementmanyG1,dcc*CGCCDesignRunsNarneIConStraintSsynth1dJ.constrs_1I-Cimpi_1ConStrS_1Out-Of-ContextModu1eR.1-fir_compi1er_0_synth_1fir_compi1er_0Name：Version：InterfaciDescriptStatUSsynthdesignCompNotstartedSynth一designComp1e1UJTc1Conso1eMessages-41ogReports凌DesignRuns2定制F1R参数第