EDA技术实验报告--硬件乐曲演奏电路设计.docx

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1、实验报告课程 EDA技术实验名称 硬件乐曲演奏电路设计第 页一、实验目的1、设计数控分频器，学习设计硬件乐曲演奏电路；2、学习使用开发板，将设计好的电路烧写进去，使其实现具体的功能；二、实验内容1、设计一个分频器，实现20M1M, 20M4HZ的分频；2、利用ROM写入梁祝的乐谱码；3、利用1中分频分得的4HZ设计一个计数器，使得读完梁祝中139个节拍后得以置零；4、设计一个译码电路，使得梁祝乐谱码可以转换成相应的音符频率；5、设计一个11位的数控分频器,使得梁祝中的每一个音符的音调得以确定；三、实验环境QuartusII 软件四、实验步骤1、设计一个分频器，实现20M1M, 20M4HZ的分

2、频；(1)实验代码:1 23 45 6789 IO 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29LIBRARY IEEE;USE IEEE .STD_LOGIC_1164. ALL;USE IEEE .STDLOGIC2UNSIGNED. ALL;H ENTITY M_20DIV IS PORT (INCLKO : IN STD_LOGIC ;CLKlMzCLK4 : OUT STD_LOGIC)；END ;S ARCHITECTURE ONE OF M_20DIV ISSIGNAL R1,R2,R3,R4 :STD_LOGI

3、C_VECTOR (7 DOTO 0)SIGNAL CX,CY,CZ,CQ : STDlLOG工C： BEGIN IM DIVISIONH PROCESS (INCLKO)BEGINH IF INCLKOEVENT AND INCLKO=,1, THENIF Rl = 9 THEN Rl=,r00000000r, ; CX= NOT CX ;HELSE R1=R1+1 ;END IF ；END IF ;CLK1M=CX ;END PROCESS ;4HZ DIVISIONH PROCESS (CX)BEGINH IF INCLKO,EVENT AND INCLKO=1 THENIF R2 =2

4、49 THEN R2=,00000000r, ;CY= NOT CY ;HELSE R2=R2+1 ;30313233343536373839404142434445464748495051END IF ;END IF ;END PROCESS ;H PROCESS (CY)BEGINH IF CY,EVENT AND CY=11, THENIF R3 =249 THEN R3=,00000000r, ; CZ=NOT CZ ;HELSE R3=R3+1 ;END IF ;END IF ;CLK4=CZ ;END PROCESS ;H PROCESS (CZ)BEGINH IF CZ,EVEN

5、T AND C=1, THENIF R4 =9 THEN R4=r,00000000rr ; CQ=NOT CQ ；HELSE R4=R4+1 ;END IF ;END IF ;CLK4 clockq3.0Currently selected device family:Cyclone IIIVH Match project/defaultFamily supports LPM_ROM only in backward-compatibility mode. Altera recommends using ALTSYNCRAM wizard.How wide should the ,q, ou

6、tput bus be?4 V bitsHow many 4-bit words of memory?256 V words将梁祝的乐谱码写入到ROM: 3 ; 01: 3 ; 02: 3; 03: 3; CM: 5; 05: 5; 06: 5;07: 6; 08: 8; 09: 8;10: 8; 11:9; 12: 6; 13: 8; 14: 5; 15: 5; 16: 12; 17: 12;18: 12; 19:15;20:13 ; 21:12; 22:10 ; 23:12; 24: 9; 25: 9; 26: 9; 27: 9; 28: 9; 29: 9;30: 9; 31:0; 32:

7、 9; 53: 9; 34: 9; 35:10; 36: 7; 37: 7; 38: 6; 39: 6;40: 5; 41: 5; 42:5;43:6; 44: 8;45:8; 46:9;47:9;48:3; 49: 3;50: 8; 51:8; 52:6;53:5; 54: 6;55:8; 56:5;57:5;58:5; 59: 5;60: 5; 61: 5 ; 62: 5; 63: 5; 64:10; 65:10; 66:10; 67:12; 68: 7; 69: 7;70: 9; 71:9; 72:6;73:8; 74: 5;75:5; 76:5;77:5;78:5; 79: 5;80:

8、 3; 81: 5 ; 82:3;83:3; 84: 5;85:6; 86:7;87:9;88:6; 89: 6;90: 6; 91:6; 92: 6;处:6； 94: 5; 95: 6; 96: 8; 97: 8; 98: 8; 99: 9;100:12 ;101:12 ;1O2:12;1O3:1O;1(M: 9; 105: 9;106:10; 107: 9;108: 8: 109: 8;110: 6 ;111:5; 112: 3;113:3; 114:3;115:3; 116:8: 117:8; 118:8; 119: 8;120: 6 ; 121:8; 122: 6;123:5; 124

9、:3;125:5; 126:6; 127:8;128:5; 129: 5;130: 5 ;131:5; 132: 5;1S3:5; 134:5; 135:5; 136:0:137:0;138:0;3、利用1中分频分得的4HZ设计一个计数器，使得读完梁祝中139个节拍后得以置零(1)实验代码:1 LIBRARY IEEE；2 USE IEEE .STD_LOGIC_1164. ALL；3 USE IEEE .STD2LOGIC2UNSIGNED. ALL；4 H ENTITY cetl38t IS -5 H PORT ( elk ： IN STD_LOGIC；6 cnt8 : OUT STD_L

10、OGIC_VECTOR (7 DOWNTO 0);7 END；8 H ARCHITECTURE one OF cetl38t IS9 SIGNAL Counter: STD_LOGIC_VECTOR (7 DOWNTO 0);10 H BEGIN11 HPROCESS(clkzCounter)12BEGIN13HIF Counter=138 THEN Counter = ,?00000000 ;14ELSIF (clk,EVENT AND elk = ,1,) THEN Counter = Counter+115END PROCESS；16 cnt8 Tone1111” UHEN ,0001r

11、, = Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone NULL;；CODE=,OOOOr,;；CDE=,0001r,;；CODE=,0010f,;；CODE=,rOOH,r;；CDE=,0101r,;；CODE=,0110,r;；CODE=,0111,r;；CDE=,0001,r;；CDE=r,0010,r;；CODE=,OOHr,;；CDE=,0101,r;；CDE=,0110r,;；CODE=,0001,r;HI_GH = 0,2047HI2GH =0； 773； H1二GH =0； 912； H工IGH = 0 ；1036； HI2GH , 0 ；1197; H工IGH , 0 ；1290； H1二GH =