EDA技术实验报告.docx

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1、EDA技术实验报告实验一 EDA实验基本设计一、实验时间：20年10月15日第六周星期六4节二、实验地点：集成电路设计实验室(一)(一教1427)三、实验目的1.熟悉ALTERA公司EDA设计工具软件Quartus II的使用方法。四、实验仪器计算机(预装QUartUS 软件)五、实验内容1 .建立工作库文件夹和编辑设计文件(1)新建一个文件夹，文件夹名为CntIOb,路径为d:cntlOb(2)输入源程序畲 VhdlLvhdI CNT10.VHD1234567891011121314151617181920212223242526272829library ieee；USE IEEE.STD

2、_LOGIC_1164.ALL;USE IEEE.STD二LoGlUUNSlGNED.ALL; ENTITY CNT10-ISS PORT (CLK,RST,EN,LOAD:IN STD_LOGIC;DATAjIN STDJOGIJVECT6r(3 DOWNTO 0);DOUT:OUT STD_L0GIC_VECT0R(3 DOWNTO 0);COOT:OUT STDjoGIQ;END CNTlO; ARCHITECTURE behav OF CNTlO ISBBEGINH PROCESS(CLK,RST,EN,LOAD)VARIABLE Q: STDjOGIjVEcToR(3 DOWNTO

3、0)； BEGINS IF RST=0 THEN Q:=(OTHERS=0);B ELSIF CLK, EVENT AND CLK=1 THENH IF EN=1, THENIF (LOAD=,0,) THEN Qj=DATA;ELSEHIF Q,0,);END IF;END IF;END IF;END IF;B IF Q=1001 THEN COUT=,1,;ELSE COUT=0,; END IF;DOUT Compile Designz Analysis & Synthesis* Fitter (Place ft Route)*B Assembler (Generate programm

4、ing file， B- TineQuest Timing AnalysisT EDANetIiStYriterJM 力 KC n/ 95 ( 14 % )/ 5/ 136 ( U ) 5l136 (1 ) 5J36 (1 X)/ 423,936 ( 0 %)/ 46 ( 0 X )/2(0)Info: The Metastability Analysis global option is set to OFF.Info: No synchronizer chains to report.Info: Design is not fully constrained for setup requi

5、rementsInfo: Design is not fully constrained for hold requirementsInfo: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 13 warningsInfo: Quartus II Full Compilation was successful. 0 errors, 18 warnings 5yMem (21)入 PwCe$ing (102) Exlralnfo ) Info (88) Warning (2) Critical Warning (12)

6、 Error Suppressed(S) Flag / Message: 0 of 227 圉 上 Location:一5.时序仿真(1)打开波形编辑器，如图所示:但 File Edit View Project Assignments Processing Tools Window HelpIlelGqgex 电eIIG C cntio三Il 屐 ,0 0. 的 IA 旷叫地中士 0 * Project NaVigator = EntityILOgiC CeLLS IDediCatW但 Waveform1.vwfCyCione L EP3C5E144C8懿 CMTIo 9 R 一&Hie向C

7、hy 国 FiIeS 逆 DeSign UnitS JTasksFlow： CompilationTaSkMz B Compile DesignA E X3A鹿鹿黑m沏外 M 英H一竺沏z-x曝AnaIySiS & SyntheSiSFitter IHaCe & RoUte)Assembler (Generate programming files) TimeQuest Timing Analysis EDA Netlist Writer(2)设置仿真时间区域(3)波形文件存盘。选择File-SaVe As命令，将以默认名为CNTlO. vwf的波 形文件存入文件夹d:cntlOb中。(4)将

8、工程CNTIO的端口信号节点选入波形编辑器中，如图所示：!但 File Edit View Project Assignments Processing Tools Window Help_ t51Il D of H S 骨 I /电电 ISJ IICNTIO三|短/0 电每 I IAI I j &EntityA Cyclone I: EP3C5E144C8LOgiC CelIS DediCatf但 Wavefoiml.vwfz14.975 ns Jj Pointer:3.9 nsInterval: -11.08 ns Start: End:心HierarChy B) FiIeS d DeSi

9、gn UnitS Tasks Flow： ICOmPiIatiOnJaSkg Compile Design申A AnalySiS & Synthesis申A Fitter (HaCe & Route) ASSembIer (Generate PrOgramming files)TimeQuest Timing AnalysisEDA Netlist Writer国 Master Time Bar: I Ilame30. Q nsNode FinderCustomize.j COUTUnassigned OutputUser entered | Include subentities ASSig

10、nmentS TyPe IInaSSigned InPUtLook in: LUNodes Found:Name一*CLK .I CreatOlUSer entered育 DATA IDATAO QDATA1 QDATA2 DDATA3 哥 DOUT pouroUnassigned Unassigned Unassigned Unassigned Unassigned Unassigned IInaSSiQnedInput GroupInputInputInputInputOutput Gro.OUtDUtUser entered User entered User entered User entered User entered User entered USer entered(5)编辑输入波形(输入激励信号)，如图所示：g Tools Window HelpI-IltS1 |臼三11减电I独IA好飞 纺电 等 嬖 *卜： IMaster Time Bar:14.975 ns 一龙脸：I 而; 色 CNTIO vwfInterval: -14.98 ns Start:彰A鹿旭那庙外ZXX2一股(6)总线数据格式设置和参数设置 Display gray code count as binary count确定 I取消